1. Field of the Invention
This invention relates to an analog-to-digital converter of the pulse width modulation type, and particularly to an incremental pulse width modulation type for generating a digital representation of the amplitude of an analog current with very low bias offset and bias drift errors. This invention is an improvement over U.S. Pat. No. 3,918,050, entitled "ANALOG-TO-DIGITAL CONVERSION APPARATUS", by A. K. Dorsman, and assigned to the same common assignee.
2. Description of the Prior Art
There are many electromagnetic accelerometer output digitizers, current digitizers, digital voltmeters and other analog-to-digital conversion devices known in the prior art for converting an analog input into a digital output. Many of these devices utilize pulse width modulated signals in converting the analog input into the digital output. The following U.S. Patents are considered representative of the existing state of the prior art.
U.S Pat. No. 3,500,109 discloses an analog-to-digital converter which sequentially switches positive and negative reference voltages and then converts these switched reference voltages into reference currents. An integrator selectively sums these reference currents with an input analog current to provide an integrator output voltage which is compared in a comparator to the voltage of a triangle wave. When the integrator output voltage is larger than the triangle wave voltage, the sum of the input analog current and a negative reference current is integrated. When the integrator output voltage is smaller than the triangle wave voltage, the sum of the input analog current and a positive reference current is integrated. The output of the comparator is a pulse width modulated signal which is proportional to the input analog signal and is utilized to sequentially control the switching of the positive and negative reference voltages. The switched reference voltages are also used to control the up and down counting of clock pulses in a reversible counter to develop a digital readout representative of the input analog signal value. There are several disadvantages inherent in this device. The pulse width output of the comparator is not synchronized with the clock pulses. This will cause readout errors. The use of two reference voltages leads to two different scale factors for the positive and negative voltage values, with a maximum of bias error occuring about a zero volt input signal. In addition, there is a further loss in scale factor linearity and accurate readout values when voltages are switched.
In U.S. Pat. No. 3,316,547, reference and analog voltages are alternately switched and converted into currents before being applied to an integrator. The integrated value of the currents is applied to a level comparator which controls the gating of clock pulses to a counter. The counter provides the digital output and also controls a flip flop which controls the switching of reference and analog voltages. There are several disadvantages associated with this device. This device appears to be capable of digitizing only one polarity of input voltage. Since the input voltage is applied only part of the time, any change in the amplitude of the input voltage during the time the reference voltage is being utilized will produce an error in the digital output. A switch shorts out the integrating capacitor in the integrator, thereby causing accumulated errors to be developed. The comparator is not triggered by the pulse generator. As a result, when the comparator changes its state, an error of up to one pulse time of the pulse generator can result. Furthermore, a voltage switching technique, with its attendant loss in scale factor linearity and loss in accurate readout values is used here.
Other voltage switching types of analog-to-digital converters are disclosed in U.S. Pat. Nos. 3,305,856; 3,458,809, and 3,488,652. Each of these converters therefore has the attendant disadvantages of loss of scale factor linearity and loss in accurate readout values.
U.S Pat. No. 3,305,856 discloses an analog-to-digital converter employing a sawtooth waveform as a switching point determining signal for a voltage comparison circuit or summer which responds to the sum of the sawtooth voltage and an integrated input signal. The comparison circuit controls the switching of a precision solid state switch to alternately apply positive and negative voltages to its output line. The output of the solid state switch is a pulse width modulated signal having a constant period and a first polarity duration proportional to the input analog voltage. Another disadvantage of this converter results from the fact that the feedback switching times of the solid state switch are not synchronized with the time base output or the means for determining the counting period of the universal counter. This limits the accuracy of the readout, since errors result from a loss of a portion of the pulse width appearing at the output of the solid state switch.
The voltage switching type of analog-to-digital converter taught in U.S. Pat. No. 3,458,809 has a constant period conversion cycle. During a first part of the cycle, a switch is enabled by clock pulses to allow a reference voltage to be passed therethrough and then converted into a reference current which is algebraically summed with an analog current at the input of an integrator. During the second part of the cycle, the switch is disabled and only the analog current is applied to the input of the integrator. The percentage of the period occupied by the first part of the cycle adjusts so that it is representative of the value of the input analog signal. A counter counts the clock pulses during one portion of the cycle in order to determine the value of the input analog signal in digital form. An additional disadvantage of this converter is that the feedback period is not synchronized with the clock pulse. Therefore, the pulse width cannot be accurately measured and large linearity errors occur.
The voltage switching type of analog-to-digital converter disclosed in U.S. Pat. No. 3,488,652 is similar to that of U.S. Pat. No. 3,500,109, except that the alternately switched positive and negative reference voltages are filtered, rather than integrated, before being summed with an analog voltage. Also, no triangle wave voltage comparison is made. Instead a comparison of the summed voltages is made with respect to ground. Since no integrator is used here, the output accuracy is relatively low.
All of the above-described patents relate to voltage switching types of analog-to-digital converters which, as discussed above, have many disadvantages. All of these patents have the common disadvantages of loss of scale factor linearity and loss in accurate readout values.
The apparatus described in the above-noted U.S. patent application Ser. No. 524,841 employs a unipolar current switching implementation which substantially minimizes the disadvantages of loss of scale factor linearity and loss in accurate readout values. That apparatus possesses very good scale factor linearity and scale factor stability (or low scale factor errors) and develops relatively accurate readout values. Scale factor errors constitute a large portion of the errors in an analog-to-digital conversion system. Although scale factor errors have been substantially minimized in that apparatus, that apparatus still inherently possesses bias offset and bias drift errors.
None of the above-discussed U.S. patents and U.S. patent application teaches an analog-to-digital converter of the incremental pulse width modulation type for generating a highly accurate digital representation of the amplitude of an analog current with low bias and low scale factor errors by selectively summing a bipolar switched precision current with the analog current as a function of the amplitude of the analog current.